1. Field of the Invention
The invention relates generally to semiconductor processing and more particularly to using field implants in BiCMOS process.
2. Description of the Prior Art
In walled-emitter type transistor structures, for example an NPN transistor 10 in FIGS. 1A and 1B, there is a problem with n-type dopants piling up at the outside edges of a p-type intrinsic base 12. Transistor 10 further comprises an n+ emitter 14, an n+ poly emitter 16, a silicide 18, a surrounding field oxidation 20, an n-type layer 22, and an n+ collector 24. Silicide 18 is not required, and is sometimes omitted in particular prior art devices. A spacer 26 and an extrinsic base 28 are shown only in FIG. 1C so that FIG. 1A is clearer. A so-called "island mask" is used early in the fabrication process of transistor 10 to create a region generally defined by an active area 30.
BiCMOS processes can be used to fabricate self-aligned bipolar transistors, such as transistor 10. A masking step is typically employed during fabrication to define the active area 30 which bounds the region of intrinsic base 12. For example, a mask of nitride is temporarily positioned over the active area 30. A field oxide region is formed to surround the active area 30. A second mask defines the patterning of N+ doped polysilicon and silicide films used for poly emitter 16. The advantages of self-aligned transistors are small layout area, small parasitic capacitances, and small base resistance.
There is at least disadvantage to fabricating bipolar transistors like transistor 10 of FIGS. 1A-1C. The intrinsic base 12 touches the field oxide 20. This constitutes the so-called "walled-emitter" transistor. It is well known that boron atoms in intrinsic base 12 will segregate into the field oxide 20 and arsenic and/or phosphorus in the n-type layer 22 will pile up adjacent to the field oxide 20. The effective base doping in the silicon adjacent to the field oxide 20 is thus lowered, and the degree of decrease cannot be controlled. Therefore, intrinsic base 12 will be more easily depleted by emitter-collector voltages and parasitic currents will result that degrade the performance of transistor 10. Such a reduction in effective base doping causes decreased and unpredictable punch-through voltage characteristics to appear between the collector 24 and emitter 14 (BVces). In high performance applications, the degradation cannot be tolerated. In lower performing, prior art applications, the degradation is not objectionable, and an economic decision can be made to tolerate, rather than fix the problem.
There have been some prior art solutions to the low BVces problem. For example, the intrinsic base doping can be increased, but this will decrease the current gain (beta) and speed (fT) of a bipolar transistor. This makes such a correction not a good choice, because the usual concern is to increase both to achieve high performance devices.
Some prior art technologies use an additional mask to increase the base doping in the silicon around the field oxide region. Referring to FIG. 2, an NPN walled-emitter transistor 40 is shown in cross section. For ease of illustration, those layers in transistor 40 that are similar to those in transistor 10 have the same element numbers. A pair of p+ skirts 42 and oxide skirts 44 are fabricated after the field oxide is grown. To do this, a second mask, which is not self-aligned, is used as an implant mask. P-type dopants (e.g., boron) are implanted, forming p+ skirts 42. An oxide is then formed on top of that, making oxide skirts 44. The result is the structure of FIG. 2 where the walled-emitter 14 has been insulated at its edges and the base 12 has been enhanced by the more highly doped p+ skirts 42. The disadvantage of this approach is, of course, one more masking step, few more processing steps, and more layout area are needed to achieve equivalent bipolar current drive levels.